{"product_id":"ds200tccag1b-ge-mark-v-analog-i-o-module","title":"DS200TCCAG1B GE Mark V Analog I\/O Module","description":"\u003cp\u003eConfigured for analog signal processing, sensor conditioning, and multi-channel terminal interfacing in Speedtronic Mark V control systems, the \u003cstrong\u003eGE DS200TCCAG1B\u003c\/strong\u003e (\u003cstrong\u003eDS200TCCA\u003c\/strong\u003e Analog I\/O Module) provides direct physical\/electrical execution.\u003c\/p\u003e\n\u003ch3\u003eHardware Specifications\u003c\/h3\u003e\n\u003cfigure class=\"table\"\u003e\n\u003ctable\u003e\n\u003cthead\u003e\n\u003ctr\u003e\n\u003cth\u003e\u003cstrong\u003eParameter\u003c\/strong\u003e\u003c\/th\u003e\n\u003cth\u003e\u003cstrong\u003eSpecification\u003c\/strong\u003e\u003c\/th\u003e\n\u003c\/tr\u003e\n\u003c\/thead\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd\u003eModel\u003c\/td\u003e\n\u003ctd\u003eDS200TCCAG1B\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eBrand\u003c\/td\u003e\n\u003ctd\u003eGeneral Electric\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eOrigin\u003c\/td\u003e\n\u003ctd\u003eUSA\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eWeight\u003c\/td\u003e\n\u003ctd\u003e0.50 kg (1.11 lbs)\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eDimensions\u003c\/td\u003e\n\u003ctd\u003eStandard Mark V Board Profile\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eOperating Temp\u003c\/td\u003e\n\u003ctd\u003e0 to 60 deg C\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003ePower Consumption\u003c\/td\u003e\n\u003ctd\u003eBoard logic power drawing \u0026lt; 12.0 W\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eOnboard Microprocessor\u003c\/td\u003e\n\u003ctd\u003e1x Intel 80196 Microprocessor\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eMemory Subsystem\u003c\/td\u003e\n\u003ctd\u003eMultiple PROM Modules\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eStatus Indicators\u003c\/td\u003e\n\u003ctd\u003e1x Side-Visible Diagnostic LED\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eInterfacing Connectors\u003c\/td\u003e\n\u003ctd\u003e2PL (TCPS Power), 3PL (COREBUS Signal), JAA\/JBB (4-20 mA I\/O), JCC\/JDD (RTD Inputs), JAR\/S\/T (TBQA Terminal), JC (Power Diagnostic), JEE (Unused)\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eOnboard Jumpers\u003c\/td\u003e\n\u003ctd\u003eJ1 (RS232 Enable\/Disable), JP2 (Oscillator Test Select), JP3 (Factory Testing Only)\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eOnboard Signal Circuits\u003c\/td\u003e\n\u003ctd\u003eDedicated RTD, Thermocouple, and Shaft Monitoring Circuits\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003ePCB Coating\u003c\/td\u003e\n\u003ctd\u003eNormal Conformal Coating\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/tbody\u003e\n\u003c\/table\u003e\n\u003c\/figure\u003e\n\u003ch3\u003eBackplane Bus \u0026amp; Firmware Architecture\u003c\/h3\u003e\n\u003cp\u003eThe DS200TCCAG1B leverages an onboard 80196 microprocessor and programmable logic devices to handle local digitizing and conditioning of incoming RTD, thermocouple, and 4-20 mA currents. Signals pass across internal high-speed headers (such as 3PL COREBUS) to optimize backplane bus communication velocity across the Mark V controller. Operating parameters and execution code are stored directly in socketed PROM modules. Firmware flash compatibility is governed via these replaceable onboard PROMs in conjunction with the host Mark V processor core, allowing deterministic execution of analog processing routines without requiring external software downloading.\u003c\/p\u003e\n\u003ch3\u003eFrequently Asked Questions\u003c\/h3\u003e\n\u003cp\u003eQ: What are the correct jumper settings for normal field operation on the DS200TCCAG1B?\u003c\/p\u003e\n\u003cp\u003eA: Jumper J1 configures the RS232 port state as needed for diagnostics, JP2 selects testing oscillator modes, and JP3 must remain in its factory default position and should not be altered during normal field operation.\u003c\/p\u003e\n\u003cp\u003eQ: How does the DS200TCCAG1B interface with external RTD and thermocouple field wiring?\u003c\/p\u003e\n\u003cp\u003eA: Field RTD signals route through terminal board TBCA into connectors JCC and JDD, while thermocouple and 4-20 mA I\/O signals pass through terminal boards CTBA and TBQA via headers JAA, JBB, and JAR\/S\/T.\u003c\/p\u003e\n\u003cp\u003eQ: Can the DS200TCCAG1B be replaced without cutting power to the Mark V panel?\u003c\/p\u003e\n\u003cp\u003eA: No. Hot-swapping is strictly prohibited; power to the core rack must be fully isolated to avoid signal corruption across the COREBUS and to prevent damage to sensitive analog front-end components.\u003c\/p\u003e\n\u003ch3\u003eField Installation Guidelines\u003c\/h3\u003e\n\u003cul\u003e\n\u003cli\u003eDisconnect all primary rack power supplies and field current loops prior to removing or installing the module.\u003c\/li\u003e\n\u003cli\u003eEnsure socketed PROM chips are firmly pressed into their sockets and oriented correctly before board installation.\u003c\/li\u003e\n\u003cli\u003eAlign all multi-pin ribbon cable connectors carefully with board header pins (JCC, JDD, 3PL, etc.) to prevent pin bending during insertion.\u003c\/li\u003e\n\u003cli\u003eMaintain shield ground continuity for all incoming RTD and thermocouple cables at designated enclosure earth buses to suppress high-frequency electrical noise.\u003c\/li\u003e\n\u003c\/ul\u003e","brand":"GE Fanuc","offers":[{"title":"Default Title","offer_id":43868763095130,"sku":"DS200TCQAG1B","price":0.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0710\/5957\/0778\/files\/DS200TCQAG1B.png?v=1787132101","url":"https:\/\/www.spareoil.com\/products\/ds200tccag1b-ge-mark-v-analog-i-o-module","provider":"SpareOil Automation","version":"1.0","type":"link"}