DS200TCCAG1B GE Mark V Analog I/O Module

Availability: 10 left in stock

Configured for analog signal processing, sensor conditioning, and multi-channel terminal interfacing in Speedtronic Mark V control systems, the GE DS200TCCAG1B...

SKU: DS200TCQAG1B

Manufacturer: GE Fanuc
Product No.: DS200TCQAG1B
Product Type: Analog I/O Modules
Product Origin: USA
Payment:T/T, Western Union
Weight: 500g
Shipping port: Xiamen
Warranty: 12 months

Description Reviews

Configured for analog signal processing, sensor conditioning, and multi-channel terminal interfacing in Speedtronic Mark V control systems, the GE DS200TCCAG1B (DS200TCCA Analog I/O Module) provides direct physical/electrical execution.

Hardware Specifications

Parameter	Specification
Model	DS200TCCAG1B
Brand	General Electric
Origin	USA
Weight	0.50 kg (1.11 lbs)
Dimensions	Standard Mark V Board Profile
Operating Temp	0 to 60 deg C
Power Consumption	Board logic power drawing < 12.0 W
Onboard Microprocessor	1x Intel 80196 Microprocessor
Memory Subsystem	Multiple PROM Modules
Status Indicators	1x Side-Visible Diagnostic LED
Interfacing Connectors	2PL (TCPS Power), 3PL (COREBUS Signal), JAA/JBB (4-20 mA I/O), JCC/JDD (RTD Inputs), JAR/S/T (TBQA Terminal), JC (Power Diagnostic), JEE (Unused)
Onboard Jumpers	J1 (RS232 Enable/Disable), JP2 (Oscillator Test Select), JP3 (Factory Testing Only)
Onboard Signal Circuits	Dedicated RTD, Thermocouple, and Shaft Monitoring Circuits
PCB Coating	Normal Conformal Coating

Backplane Bus & Firmware Architecture

The DS200TCCAG1B leverages an onboard 80196 microprocessor and programmable logic devices to handle local digitizing and conditioning of incoming RTD, thermocouple, and 4-20 mA currents. Signals pass across internal high-speed headers (such as 3PL COREBUS) to optimize backplane bus communication velocity across the Mark V controller. Operating parameters and execution code are stored directly in socketed PROM modules. Firmware flash compatibility is governed via these replaceable onboard PROMs in conjunction with the host Mark V processor core, allowing deterministic execution of analog processing routines without requiring external software downloading.

Frequently Asked Questions

Q: What are the correct jumper settings for normal field operation on the DS200TCCAG1B?

A: Jumper J1 configures the RS232 port state as needed for diagnostics, JP2 selects testing oscillator modes, and JP3 must remain in its factory default position and should not be altered during normal field operation.

Q: How does the DS200TCCAG1B interface with external RTD and thermocouple field wiring?

A: Field RTD signals route through terminal board TBCA into connectors JCC and JDD, while thermocouple and 4-20 mA I/O signals pass through terminal boards CTBA and TBQA via headers JAA, JBB, and JAR/S/T.

Q: Can the DS200TCCAG1B be replaced without cutting power to the Mark V panel?

A: No. Hot-swapping is strictly prohibited; power to the core rack must be fully isolated to avoid signal corruption across the COREBUS and to prevent damage to sensitive analog front-end components.

Field Installation Guidelines

Disconnect all primary rack power supplies and field current loops prior to removing or installing the module.
Ensure socketed PROM chips are firmly pressed into their sockets and oriented correctly before board installation.
Align all multi-pin ribbon cable connectors carefully with board header pins (JCC, JDD, 3PL, etc.) to prevent pin bending during insertion.
Maintain shield ground continuity for all incoming RTD and thermocouple cables at designated enclosure earth buses to suppress high-frequency electrical noise.

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