The YOKOGAWA F3BU13-0N, also cataloged as the F3BU130N Base Module Assembly, operates as a dedicated hardware component for module housing and signal bus distribution within FA-M3 PLC system platforms.
| Parameter | Specification |
|---|---|
| Model | F3BU13-0N |
| Brand | YOKOGAWA |
| Origin | Japan |
| Weight | 1.5 kg |
| Dimensions | 450 × 100 × 126 mm |
| Operating Temp | 0 deg C to +55 deg C |
| Power Consumption | Passive bus distribution |
| Total Slots | 13 |
| Bus Type | FA-M3 Proprietary High-Speed |
The F3BU13-0N serves as the physical foundation for the FA-M3 backplane, providing a deterministic communication path for data exchange between the CPU, I/O modules, and communication interfaces. The assembly features a high-density, multi-layer printed circuit backplane designed for low-impedance signal routing and crosstalk suppression. To ensure consistent system performance, the backplane bus supports synchronized backplane bus communication velocity management, which prevents signal reflection and packet corruption during high-frequency data transactions across all 13 slots. The integrated power distribution rails are engineered to maintain stable voltage levels for all mounted modules, minimizing thermal stress on the component logic.
Q: Does the F3BU13-0N include an integrated power supply?
A: No. The base unit acts as a passive backplane for module interconnection. The power supply (e.g., F3PU30-0S) must be installed in the designated leftmost slot of the rack to provide power to the backplane.
Q: Can modules be inserted or removed while the rack is powered?
A: No. The F3BU13-0N does not support hot-swapping. All power must be removed from the base unit prior to the insertion or removal of any PLC module to prevent electrical damage to the backplane connector pins.
Q: Is the backplane bus compatible with all FA-M3 modules?
A: The backplane is compatible with the standard FA-M3 module series. Always verify module-to-slot compatibility in the system configuration software to ensure correct addressing and bus bandwidth allocation.
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